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ice-port is a trademark of analog devices, inc. dsp microcomputer adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o.box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 analog devices, inc. all rights reserved. performance features up to 19 ns instruction cycle time, 52 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows du al operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissi- pation with 400 clkin cycle recovery from power-down condition low power dissipation in idle mode integration features adsp-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions up to 160k bytes of on-chip ram, configured up to 32k words program memory ram up to 32k words data memory ram dual-purpose program memory for both instruction and data storage independent alu, multiplier/a ccumulator, and barrel shifter computational units 2 independent data address generators powerful program sequencer pr ovides zero overhead loop- ing conditional instruction execution programmable 16-bit interval timer with prescaler 100-lead lqfp and 144-ball bga system interface features 16-bit internal dma port for high-speed access to on-chip memory (mode selectable) 4m-byte memory interface for storage of data tables and pro- gram overlays (mode selectable) 8-bit dma to byte memory for transparent program and data memory transfers (mode selectable) programmable memory strobe and separate i/o memory space permits glueless system design programmable wait state generation 2 double-buffered serial port s with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte- wide external memory, for example, eprom, or through internal dma port 6 external interrupts 13 programmable flag pins prov ide flexible system signaling uart emulation through soft ware sport reconfiguration ice-port emulator interface supports debugging in final systems figure 1. functional block diagram arithmetic units shifter mac alu program memory address data memory address program memory data data memory data power-down control memory program memory up to 32k 24-bit external address bus external data bus byte dma controller sport0 serial ports sport1 programmable i/o and flags timer host mode or external data bus internal dma port dag1 data address generators dag2 program sequencer adsp-2100 base architecture data memory up to 32k 16-bit full memory mode
rev. c | page 2 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l table of contents performance features ............................................... 1 integration features ................................................. 1 system interface features ........................................... 1 table of contents ..................................................... 2 revision history ...................................................... 2 general description ................................................. 3 architecture overview ........................................... 3 modes of operation .............................................. 4 interrupts ........................................................... 5 low power operation ............................................ 6 system interface ................................................... 7 reset .................................................................. 8 memory architecture ............................................ 8 bus request and bus grant ................................... 13 flag i/o pins ..................................................... 13 instruction set description ................................... 14 development system ........................................... 14 additional information ........................................ 16 pin descriptions .................................................... 17 memory interface pins ......................................... 18 terminating unused pins ..................................... 19 specifications ........................................................ 21 operating conditions ........................................... 21 electrical characteristics ....................................... 21 absolute maximum ratings ................................... 22 package information ............................................ 22 esd sensitivity ................................................... 22 timing specifications ........................................... 22 power supply current .......................................... 36 power dissipation ............................................... 37 output drive currents ......................................... 40 power-down current ........................................... 41 capacitive loading C adsp-2184l, adsp-2186l ... ..... 42 capacitive loading C adsp-2185l, adsp-2187l ... ..... 42 test conditions .................................................. 43 environmental conditions .................................... 43 lqfp package pinout ........................................... 44 bga package pinout ............................................ 45 outline dimensions ................................................ 46 surface mount design .......................................... 47 ordering guide ..................................................... 47 revision history 1/08rev. c this revision of the adsp-2184l/adsp-2185l/ adsp-2186l/adsp-2187l processor data sheet combines the adsp-2184l, adsp-2185l, adsp-2186l, and adsp-2187l. this version also contains new rohs compliant packages.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 3 of 48 | january 2008 general description the adsp-218xl series consists of four single chip microcom- puters optimized for digital signal processing applications. the functional block diagram for the adsp-218xl series members appears in figure 1 on page 1 . all series members are pin-com- patible and are differentiated solely by the amount of on-chip sram. this feature, combined with adsp-21xx code compati- bility, provides a great deal of flexibility in the design decision. specific family members are shown in table 1 . adsp-218xl series members co mbine the adsp -2100 family base architecture (three comput ational units, data address gen- erators, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. adsp-218xl series members inte grate up to 160k bytes of on- chip memory configured as up to 32k words (24-bit) of pro- gram ram, and up to 32k words (16-bit) of data ram. power- down circuitry is also provided to meet the low power needs of battery-operated portable equipm ent. the adsp-218xl is avail- able in 100-lead lqfp and 144-ball bga packages. fabricated using high-speed, low-power, cmos processes, adsp-218xl series members oper ate with a 19 ns instruction cycle time (adsp-2185l and adsp-2187l) or a a 25 ns instruc- tion cycle time (adsp-2184l and adsp-2186l). every instruction can execute in a single processor cycle. the adsp-218xls flexible arch itecture and comprehensive instruction set allow the proce ssor to perform multiple opera- tions in parallel. in one proc essor cycle, adsp-218xl series members can: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation this takes place while the processor continues to: ? receive and transmit data through the two serial ports ? receive and/or transmit data through the internal dma port ? receive and/or transmit data through the byte dma port ? decrement timer architecture overview the adsp-218xl series instructio n set provides flexible data moves and multifunction (one or two data moves with a com- putation) instructions. every instruction can be executed in a single processor cycle. the adsp -218xl assembly language uses an algebraic syntax for ease of coding and readability. a com- prehensive set of development tools supports program development. the functional block diagram is an overall block diagram of the adsp-218xl series. th e processor contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the comp utational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division pr imitives are also supported. the mac performs single-cycle mult iply, multiply/add, and multi- ply/subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denor- malization, and derive exponent operations. the shifter can be used to effi ciently implement numeric format control, including multiword and block floating-point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequence r supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stac ks, adsp-218xl series members execute looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and pro- gram memory). each dag mainta ins and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possi- ble modify registers. a length va lue may be associated with each pointer to implement automatic modulo addressing for circular buffers. five internal buses provide efficient data transfer: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus table 1. adsp-218xl dsp microcomputer family device program memory (k words) data memory (k words) adsp-2184l 4 4 adsp-2185l 16 16 adsp-2186l 8 8 adsp-2187l 32 32
rev. c | page 4 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/ o memory space also share the external buses. program memory can store both instructions and data, permit- ting adsp-218xl series members to fetch two operands in a single cycle, one from program memory and one from data memory. adsp-218xl series me mbers can fetch an operand from program memory and the next instruction in the same cycle. in lieu of the address and data bus for external memory connec- tion, adsp-218xl series members can be configured for 16-bit internal dma port (idma port) connection to external sys- tems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsps on-chi p program and data ram. an interface to low cost, byte-wide memory is provided by the byte dma port (bdma port). th e bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with pro- grammable wait state generation . external devices can gain control of external buses with bus request/grant signals (br , bgh , and bg ). one execution mode (go mode) allows the adsp-218xl to continue runnin g from on-chip memory. nor- mal execution mode requires the processor to halt while buses are granted. adsp-218xl series members can re spond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (sport), the bdma port, and the power-down circuitry. there is also a mas- ter reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hard- ware and a wide variety of fram ed or frameless data transmit and receive modes of operation. each serial port can generate an internal programmable serial clock or accept an external serial clock. adsp-218xl series members provid e up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an in put flag and an output flag. in addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. a programmable interval timer ge nerates periodic interrupts. a 16-bit count register (tcount) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of th e count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports adsp-218xl series me mbers incorporate two complete syn- chronous serial ports (spo rt0 and sport1) for serial communications and mult iprocessor communication. following is a brief list of th e capabilities of the adsp-218xl sports. for additional information on serial ports, refer to the adsp-218x dsp hardware reference . ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and transmit sections. sections run in a frameless mode or with frame synchronization signals in ternally or externally gen- erated. frame sync signals are active high or inverted, with either of two pulse widths and timings. ? sports support serial data word lengths from 3 bits to 16 bits and provide optional a-law and -law companding, according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated afte r a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24-word or 32-word, time-division multi- plexed, serial bitstream. ? sport1 can be configured to have two external interrupts (irq0 and irq1 ) and the fi and fo signals. the internally generated serial clock may still be used in this configuration. modes of operation the adsp-218xl series modes of operation appear in table 2 . only the adsp-2187l prov ides mode d operation setting memory mode memory mode selection for th e adsp-218xl series is made during chip reset through the use of the mode c pin. this pin is multiplexed with the dsps pf2 pin, so care must be taken in how the mode selection is made . the two methods for selecting the value of mode c ar e active and passive. passive configuration passive configuration involves the use of a pull-up or pull- down resistor connected to the mode c pin. to minimize power consumption, or if the pf2 pin is to be used as an output in the dsp application, a weak pull-up or pull-down resistance, on the order of 10 k , can be used. this value should be sufficient to pull the pin to the desired level an d still allow the pin to operate as a programmable flag output without undue strain on the pro- cessors output driver. for minimum power consumption
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 5 of 48 | january 2008 during power-down, reconfigure pf 2 to be an input, as the pull- up or pull-down resistance will hold the pin in a known state, and will not switch. active configuration active configuration involves th e use of a three-statable exter- nal driver connected to the mode c pin. a drivers output enable should be connec ted to the dsps reset signal such that it only drives the pf2 pin when reset is active (low). when reset is deasserted, the driver sh ould be three-state, thus allowing full use of the pf2 pin as either an input or output. to minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. this ensures that th e pin will be held at a constant level, and will not oscillate should the three-state drivers level hover around the logic switching point. idma ack configuration (adsp-2187l only) mode d = 0 and in host mode: iack is an active, driven signal and cannot be wire-ored. mode d = 1 and in host mode: iack is an open drain and requir es an external pull-down, but multiple iack pins can be wire-ored together. interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. adsp-218xl series members prov ide four dedica ted external interrupt input pins: irq2 , irql0 , irql1 , and irqe (shared with the pf7C4 pins). in addi tion, sport1 may be reconfig- ured for irq0 , irq1 , fi, and fo, for a total of six external interrupts. the adsp-218xl also supports internal interrupts from the timer, the byte dma port, the two serial ports, soft- ware, and the power-down control circuit. the interrupt levels are internally prioritized and individually maskable (except power-down and reset). the irq2 , irq0 , and irq1 input pins can be programmed to be either level- or edge-sensitive. irql0 and irql1 are level-sensitive and irqe is edge-sensitive. the priorities and vector addresses of all interrupts are shown in table 3 . interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. inter- rupts can be masked or unmask ed with the imask register. table 2. modes of operation mode d 1 mode c mode b mode a booting method x 0 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in full memory mode. 2 x 0 1 0 no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full me mory mode. bdma can still be used, but the processor does not automatically use or wait for these operations. 0 1 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode. iack has active pull-down. (requires additional hardware.) 0 1 0 1 idma feature is used to load any internal memory as desired. program execution is held off until the host writes to internal program memory location 0. chip is configured in host mode. iack has active pull-down. 2 1 1 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode; iack requires external pull-down. (requires additional hardware.) 1 1 0 1 idma feature is used to load any internal memory as desired. program execution is held off until the host writes to internal program memory location 0. chip is configured in host mode. iack requires external pull-down. 2 1 mode d applies to the ad sp-2187l processor only. 2 considered as standard operating settings. using these config urations allows for easier design and better memory management. table 3. interrupt priority an d interrupt vector addresses source of interrupt interrupt vector address (hex) reset (or power-up with pucr = 1) 0x0000 (highest priority) power-down (nonmaskable) 0x002c irq2 0x0004 irql1 0x0008 irql0 0x000c sport0 transmit 0x0010 sport0 receive 0x0014 irqe 0x0018 bdma interrupt 0x001c sport1 transmit or irq1 0x0020 sport1 receive or irq0 0x0024 timer 0x0028 (lowest priority)
rev. c | page 6 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the power-down interrupt is nonmaskable. adsp-218xl series members mask all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, ic ntl, controls interrupt nest- ing and defines the irq0 , irq1 , and irq2 external interrupts to be either edge- or level-sensitive. the irqe pin is an external edge-sensitive interrupt and ca n be forced and cleared. the irql0 and irql1 pins are external level sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preser ve the processor status and are automatically maintained during interrupt handling. the stacks are 12 levels deep to allow interr upt, loop, and subroutine nest- ing. the following instructions allow global enable or disable servicing of the interrupts (inc luding power-down), regardless of the state of imask: ena ints; dis ints; disabling the interrupts does not affect serial port autobuffering or dma. when the processor is reset, interrupt servicing is enabled. low power operation adsp-218xl series members have three low-power modes that significantly reduce the power di ssipation when the device oper- ates under standby conditions. these modes are: ? power-down ?idle ? slow idle the clkout pin may also be di sabled to reduce external power dissipation. power-down adsp-218xl series members have a low-power feature that lets the processor enter a very low- power dormant state through hardware or software control. fo llowing is a brief list of power- down features. refer to the adsp-218x dsp hardware refer- ence , system interface chapter, for detailed information about the power-down feature. ? quick recovery from power- down. the processor begins executing instructions in as few as 400 clkin cycles. ? support for an externally ge nerated ttl or cmos proces- sor clock. the external clock can continue running during power-down without affecting the lowest power rating and 400 clkin cycle recovery. ? support for crystal operation includes disabling the oscilla- tor to save power (the pr ocessor automatically waits approximately 4096 clkin cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 400 clkin cycle start-up. ? power-down is initiated by either the power-down pin (pwd ) or the software power-do wn force bit. interrupt support allows an unlimited nu mber of instructions to be executed before optionally powering down. the power- down interrupt also can be used as a nonmaskable, edge- sensitive interrupt. ? context clear/save control allo ws the processor to continue where it left off or start with a clean context when leaving the power-down state. ?the reset pin also can be used to terminate power-down. ? power-down acknowledge pin (pwdack) indicates when the processor has entered power-down. idle when the adsp-218xl is in the idle mode, the processor waits indefinitely in a low-power st ate until an interrupt occurs. when an unmasked interrupt occu rs, it is serviced; execution then continues with the instruct ion following the idle instruc- tion. in idle mode idma, bdma , and autobuffer cycle steals still occur. slow idle the idle instruction is enhanc ed on adsp-218xl series mem- bers to let the processors internal clock signal be slowed, further reducing power consumption. the reduced clock frequency, a programmable fraction of the norm al clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is: idle (n); where n = 16, 32, 64, or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processo rs other internal clock signals, such as sclk, clkout, and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processors internal clock an d thus its response time to incoming interrupts. the one-cycl e response time of the stan- dard idle state is increased by n, the clock divisor. when an enabled interrupt is received, adsp-218xl se ries members remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processo rs reduced internal clock rate. under these conditions, interrupts must not be generated at a
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 7 of 48 | january 2008 faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 2 shows typical basic system configurations with the adsp-218xl series, two serial devices, a byte-wide eprom, and optional external program and data overlay memories (mode-selectable). programmable wait state generation allows the processor to connect easily to slow peripheral devices. adsp-218xl series members also provide four external inter- rupts and two serial ports or si x external interrupts and one serial port. host memory mode a llows access to the full external data bus, but limits addressing to a single address bit (a0). through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. clock signals adsp-218xl series members can be clocked by either a crystal or a ttl-compatible clock signal. the clkin input cannot be halted, changed during operation, nor operated below the specified frequency during normal oper- ation. the only exception is while the processor is in the power-down state. for addition al information, refer to the adsp-218x dsp hardware reference , for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is connected to the processors clkin input. when an external clock is used, the xtal pin must be left unconnected. adsp-218xl series members use an input clock with a fre- quency equal to half the instru ction rate; a 40 mhz input clock yields a 12.5 ns processor cycl e (which is equivalent to 80 mhz). normally, instructions are executed in a single pro- cessor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because adsp-218xl series memb ers include an on-chip oscil- lator circuit, an external crysta l may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 3 . capacitor values are dependent on crystal type and shou ld be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor-grade crystal shou ld be used. to provide an adequate feedback path around the internal amplifier circuit, place a resistor in parallel with the circuit, as shown in figure 3 . a clock output (clkout) signal is generated by the processor at the processors cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. figure 2. basic system interface i n s e r t s y s t em i n t erf a ce d i a g r a m h er e 1/2 cloc or crystal fl02 cli tal serial device scl1 rfs1 or irq0 ts1 or irq1 dt1 or o dr1 or i sport1 serial deice a0a21 data bte memor io space peripherals data addr data addr 20 locations oerla memor two k pm segments d20 a10 d2 a100 d1 d21 a10 1 2 sclk0 rs0 ts0 dt0 dr0 sport0 data20 adsp21xl cs cs 12 clock or crstal clkin tal l02 serial deice sclk1 rs1 or ir q0 ts1 or irq1 dt1 or o dr1 or i sport1 1 idma port ird d is d iald iack d iad10 serial deice sclk0 rs0 ts0 dt0 dr0 sport0 1 1 a0 data2 ioms bms dms cms br bg bgh pwd pwdack host memor mode ll memor mode mode dp mode cp2 mode bp1 mode ap0 irq2 p irqe p irql0 p mode dp mode cp2 mode bp1 mode ap0 wr rd sstem interace or controller irq2 p irqe p irql0 p irql1 p ioms bms pms cms br bg bgh pwd pwdack wr rd adsp21xl dms two k dm segments pms addr10 irql1 p iwr d note: mode d applies to the adsp-2187l processor only
rev. c | page 8 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l reset the reset signal initiates a master reset of the adsp-218xl. the reset signal must be assert ed during the power-up sequence to assure prop er initialization. reset during initial power-up must be held long enou gh to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this power-up sequence, the reset signal should be held low. on any subsequent resets, the reset signal must meet the mini- mum pulse width specification (t rsp ). the reset input contains some hysteresis; however, if an rc circuit is used to generate the reset signal, the use of an exter- nal schmitt trigger is recommended. the master reset sets all intern al stack pointers to the empty stack condition, masks all interrupts, and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. the first instruction is fetched from on- chip program memory locati on 0x0000 once boot loading completes. memory architecture the adsp-218xl series provides a variety of memory and peripheral interface options. the key functional groups are pro- gram memory, data memory, byte memory, and i/o. refer to figure 4 through figure 7 for pm and dm memory allocations in the adsp-218xl series. program memory program memory (full memory mode) is a 24-bit-wide space for storing both in struction opcodes and data. the member dsps of this series have up to 32k words of program memory ram on chip, and the capability of accessing up to two 8k external memory overlay spaces , using the external data bus. program memory (host mode) allo ws access to all internal memory. external overlay access is limited by a single external address line (a0). external progra m execution is not available in host mode due to a restricted data bus that is only 16 bits wide. data memory data memory (full memory mode ) is a 16-bit-wide space used for the storage of data variables and for memory-mapped con- trol registers. the adsp-218xl series has up to 32k words of data memory ram on-chip. part of this space is used by 32 memory-mapped registers. support also exists for up to two 8k external memory overlay spaces through the external data bus. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. data memory (host mode) allows access to all internal mem- ory. external overlay access is limited by a single external address line (a0). figure 3. external crystal connections clkin clkout xtal dsp 1m figure 4. adsp-2184 memory architecture program memory pm overlay 1,2 (external pm) internal pm pm overlay 0 (reserved) reserved modeb = 0 0x3fff 0x2000 0x0000 0x0fff 0x1000 0x1fff 0x3fff 0x2000 0x0000 0x3fe0 0x3fdf 0x3000 0x2fff 0x1fff data memory dm overlay 1,2 (external dm) internal dm 32 memory-mapped control registers 4064 reserved words dm overlay 0 (reserved) program memory reserved external pm modeb = 1 0x3fff 0x2000 0x0000 0x1fff
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 9 of 48 | january 2008 figure 5. adsp-2185 memory architecture figure 6. adsp-2186 memory architecture figure 7. adsp-2187 memory architecture program memory pm overlay 1,2 (external pm) internal pm pm overlay 0 (internal pm) modeb = 0 0x3fff 0x2000 0x0000 0x1fff 0x3fff 0x2000 0x0000 0x3fe0 0x3fdf 0x1fff data memory dm overlay 1,2 (external dm) internal dm 32 memory-mapped control registers dm overlay 0 (internal dm) program memory reserved external pm modeb = 1 0x3fff 0x2000 0x0000 0x1fff program memory pm overlay 1,2 (external pm) internal pm pm overlay 0 (reserved) modeb = 0 0x3fff 0x2000 0x0000 0x1fff 0x3fff 0x2000 0x0000 0x3fe0 0x3fdf 0x1fff data memory dm overlay 1,2 (external dm) internal dm 32 memory-mapped control registers dm overlay 0 (reserved) program memory reserved external pm modeb = 1 0x3fff 0x2000 0x0000 0x1fff program memory pm overlay 1,2 (external pm) internal pm pm overlay 0,4,5 (internal pm) modeb = 0 0x3fff 0x2000 0x0000 0x1fff 0x3fff 0x2000 0x0000 0x3fe0 0x3fdf 0x1fff data memory dm overlay 1,2 (external dm) internal dm 32 memory-mapped control registers dm overlay 0,4,5 (internal dm) program memory reserved external pm modeb = 1 0x3fff 0x2000 0x0000 0x1fff
rev. c | page 10 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l i/o space (full memory mode) adsp-218xl series members support an additional external memory space called i/o space. this space is designed to sup- port simple connections to periph erals (such as data converters and external registers) or to bu s interface asic data registers. i/o space supports 2048 locations of 16-bit wide data. the lower eleven bits of the external address bus are used; the upper three bits are undefined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated 3-bit wait state registers, iowait0C3 as shown in figure 8 , which specify up to seven wait states to be automatically generated for each of four regions. the wait states act on address ranges, as shown in table 6 . note: in full memory mode, all 2048 locations of i/o space are directly addressable. in host memory mode, only address pin a0 is available; therefore, additi onal logic is required externally to achieve complete addressa bility of the 2048 i/o space locations. composite memory select adsp-218xl series me mbers have a prog rammable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is generated to have the same timing as each of the individual memory select signals (pms , dms , bms , ioms ) but can com- bine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is asserted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of th e memory, and use either dms or pms as the additional address bit. the cms pin functions like the other memory select signals with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits default to 1 at reset, except the bms bit. table 4. pmovlay bits processor pmovlay memory a13 a12C0 adsp-2184l no internal overlay region not applicable not applicable not applicable adsp-2185l 0 internal overlay not applicable not applicable adsp-2186l no internal overlay region not applicable not applicable not applicable adsp-2187l 0, 4, 5 internal overlay not applicable not applicable all processors 1 external overlay 1 0 13 lsbs of address between 0x2000 and 0x3fff all processors 2 external overlay 2 1 13 lsbs of address between 0x2000 and 0x3fff table 5. dmovlay bits processor dmovlay memory a13 a12C 0 adsp-2184l no internal overlay region not applicable not applicable not applicable adsp-2185l 0 internal overlay not applicable not applicable adsp-2186l no internal overlay region not applicable not applicable not applicable adsp-2187l 0, 4, 5 internal overlay not applicable not applicable all processors 1 external overlay 1 0 13 lsbs of address between 0x0000 and 0x1fff all processors 2 external overlay 2 1 13 lsbs of address between 0x0000 and 0x1fff table 6. wait states address range wait state register 0x000C0x1ff iowait0 0x200C0x3ff iowait1 0x400C0x5ff iowait2 0x600C0x7ff iowait3 figure 8. wait state control register dwait iowait3 iowait2 iowait1 iowait0 dm(0x3ffe) wait state control 0111111111111111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 11 of 48 | january 2008 see figure 9 and figure 10 for illustration of the programmable flag and composite control register and the system control register. byte memory select the adsp-218xls bms disable feature combined with the cms pin allows use of multiple memories in the byte memory space. for example, an eprom could be attached to the bms select, and a flash memory could be connected to cms . because at reset bms is enabled, the eprom would be used for booting. after booting, software could disable bms and set the cms sig- nal to respond to bms , enabling the flash memory. byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bd ma feature. the byte memory space consists of 256 pages, each of which is 16k 8bits. the byte memory space on th e adsp-218xl series supports read and write operations as well as four different data formats. the byte memory uses data bits 15C8 for data. the byte mem- ory uses data bits 23C16 and addr ess bits 13C0 to create a 22-bit address. this allows up to a 4 megabit 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register. byte memory dma (bdma, full memory mode) the byte memory dma controller ( figure 11 ) allows loading and storing of program instruct ions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processo r is operating normally and steals only one dsp cycle per 8- , 16-, or 24-bit word transferred. the bdma circuit supports four di fferent data formats that are selected by the btype register field. the appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. table 7 shows the data formats supported by the bdma circuit. unused bits in the 8-bit data me mory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starti ng address for the external byte memory space. the 8-bit bmpage register specifies the start- ing page for the external byte me mory space. the bdir register field selects the direction of the transfer. finally, the 14-bit bwcount register specifies th e number of dsp words to transfer and initiates th e bdma circuit transfers. bdma accesses can cross page bo undaries during sequential addressing. a bdma interrupt is generated on the completion of the number of tr ansfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is gener- ated. the bmpage and bead registers must not be accessed by the dsp during bdma operations. the source or destination of a bdma transfer is always on-chip program or data memory. when the bwcount register is written with a nonzero value the bdma circuit starts executing byte memory accesses with wait states set by bmwait. th ese accesses continue until the count reaches zero. when enou gh accesses have occurred to figure 9. programmable flag and composite control register figure 10. system control register bmwait cmssel 0 = disable cms 1 = enable cms dm(0x3fe6) pftype 0=input 1=output (where bit: 11-iom, 10-bm, 9-dm, 8-pm) 0111101100000000 1514131211109876543210 programmable flag and composite select control reserved reserved,always set to 0 sport0 enable 0=disable 1 = enable dm(0x3fff) system control sport1 enable 0 = disable 1 = enable sport1 configure 0=fi,fo,irq0,irq1,sclk 1=sport1 disable bms 0 = enable bms 1=disablebms pwait program memory wait states 0000010000000111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 note: reserved bits are shown on a gray field. these bits should always be written with zeros. reserved set to 0 figure 11. bdma control register table 7. data formats btype internal memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs bdma control bmpage btype bdir 0=loadfrombm 1=storetobm bcr 0 = run during bdma 1 = halt during bdma 0000000000001000 15 14 13 12 111098 76543210 dm (0x3fe3) bdma overlay bits (see table 12)
rev. c | page 12 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l create a destination word, it is transferred to or from on-chip memory. the transfer takes on e dsp cycle. dsp accesses to external memory have pr iority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether the pro- cessor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue opera- tions. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesse s are occurring, to clear the context of the processor, and st art execution at address 0 when the bdma accesses have completed. the bdma overlay bits specify the ovlay memory blocks to be accessed for internal memory. set these bits as indicated in figure 11 . note: bdma cannot access extern al overlay memory regions 1 and 2. the bmwait field, which has 3 bits on adsp-218xl series members, allows selection of up to 7 wait states for bdma transfers. internal memory dma port (idma port; host memory mode) the idma port provides an ef ficient means of communication between a host system and adsp-218xl series members. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word over- head. the idma port cannot, howe ver, be used to write to the dsps memory-mapped control registers. a typical idma transfer process is shown as follows: 1. host starts idma transfer. 2. host checks iack control line to see if the dsp is busy. 3. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selec- tion into the dsps idma control registers. if bit 15 = 1, the values of bits 7C0 repres ent the idma overlay; bits 14C8 must be set to 0. if bit 15 = 0, the value of bits 13C0 represent the starting address of internal memory to be accessed and bit 14 reflects pm or dm for access. set iddmovlay and idpmovlay bits in the idma over- lay register as indicted in table 8 . 4. host uses is and ird (or iwr ) to read (or write) dsp internal memory (pm or dm). 5. host checks iack line to see if the dsp has completed the previous idma operation. 6. host ends idma transfer. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is com- pletely asynchronous and can be written while the adsp-218xl is operating at full speed. the dsp memory address is latched and then automatically incremented after each idma transaction. an external device can therefore access a block of sequentially ad dressed memory by specifying only the starting address of the block. this increases throughput as the addre ss does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle. when the ac knowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the addre ss specifies an on-chip memory location, the destination type spec ifies whether it is a dm or pm access. the falling edge of the idma address latch signal (ial) or the missing edge of th e idma select signal (is ) latches this value into the idmaa register. once the address is stored, data can be read from, or written to, the adsp-218xls on-c hip memory. assertin g the select line (is ) and the appropriate read or write line (ird and iwr respectively) signals the adsp-218xl that a particular transac- tion is required. in either case , there is a one-processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, th e latched address is automati- cally incremented, and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation. asserting the idma port select (is ) and address latch enable (ial) directs the adsp-218xl to write the address onto the iad14C0 bus into the id ma control register ( figure 12 ). if bit 15 is set to 0, idma latches the address. if bit 15 is set to 1, idma latches into the ovlay re gister. this register, also shown in figure 12 , is memory-mapped at address dm (0x3fe0). note that the latche d address (idmaa) cannot be read back by the host. the idma overlay register applies to the adsp-2187l processor only. when bit 14 in 0x3fe7 is set to zero, short reads use the timing shown in figure 26 on page 34 . when bit 14 in 0x3fe7 is set to 1, timing in figure 27 on page 35 applies for short reads in short read only mode. set iddmovlay and idpmovlay bits in the idma overlay regist er as indicated in table 8 . refer to the adsp-218x dsp hardware reference for additional details. table 8. idma/bdma overlay bits processor idma/bdma pmovlay idma/bdma dmovlay adsp-2184l 0 0 adsp-2185l 0 0 adsp-2186l 0 0 adsp-2187l 0, 4, 5 0, 4, 5
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 13 of 48 | january 2008 note: in full memory mode, all locations of 4m-byte memory space are directly addressable. in host memory mode, only address pin a0 is available, requiring additional external logic to provide address information for the byte. bootstrap loading (booting) adsp-218xl series members have two mechanisms to allow automatic loading of the internal program memory after reset. the method for booting is contro lled by the mode a, mode b, and mode c configuration bits. when the mode pins specify bdma booting, the adsp-218xl initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the following defaults when bdma booting is specified: the bdir, bmpage, biad, and bead registers are set to 0, the btype register is set to 0 to specify program memory 24-bit words, and the bwcount register is set to 32. this causes 32 words of on- chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes pro- gram execution to be held off un til all 32 words are loaded into on-chip program memory. executio n then begins at address 0. the adsp-2100 family developm ent software (revision 5.02 and later) fully supports the bdma booting feature and can generate byte memory space-compatible boot code. the idle instruction can also be used to allow the processor to hold off execution while bootin g continues through the bdma interface. for bdma accesse s while in host mode, the addresses to boot memory must be constructed externally to the adsp-218xl. the only memory address bi t provided by the processor is a0. idma port booting adsp-218xl series members can also boot programs through its internal dma port. if mode c = 1, mode b = 0, and mode a = 1, the adsp-218xl boots from the idma port. idma feature can load as much on-chip memory as desired. program execu- tion is held off until the host writes to on-chip program memory location 0. bus request and bus grant adsp-218xl series members can re linquish control of the data and address buses to an extern al device. when the external device requires access to memory, it asserts the bus request (br ) signal. if the adsp-218xl is not performing an external memory access, it responds to the active br input in the follow- ing processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, ? asserting the bus grant (bg ) signal, and ? halting program execution. if go mode is enabled, the adsp-218xl will no t halt program execution until it enco unters an instruction that requires an external memory access. if an adsp-218xl series member is performing an external memory access when the exte rnal device asserts the br signal, it will not three-state the memory interfaces nor assert the bg sig- nal until the processor cycle af ter the access completes. the instruction does not need to be completed when the bus is granted. if a single instructio n requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, re-enables the output drivers, and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when an adsp-218xl series member requires the external bus for a memory or bdma access, but is stopped. the other device can re lease the bus by deasserting bus request. once the bus is rele ased, the adsp-218xl deasserts bg and bgh and executes the external memory access. flag i/o pins adsp-218xl series members have eight general-purpose pro- grammable input/output flag pi ns. they are controlled by two memory-mapped registers. the pftype register determines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the adsp-218xls clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, adsp-218xl series members have five fixed-mode flag s, fi, fo, fl0, fl1, and fl2. fl0 to fl2 are dedicated output flags. fi and fo are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2, and pf 3 are also used for device con- figuration during reset. figure 12. idma ovlay/control registers idm a ove rlay dm (0x3fe7) reserved set to 0 iddmovlay idpmovlay 000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 short read only 0 = disable 1 = enable idma control (u = undefined at reset) dm (0x3fe0) idmaa address uuuuuuuuuuuuuuu 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 idmad destination memory type 0=pm 1=dm note: reserved bits are shown on a gray field. these bits should always be written with zeros. 0 reserved set to 0 0 reserved set to 0
rev. c | page 14 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l instruction set description the adsp-218xl series assembly language instruction set has an algebraic syntax that was de signed for ease of coding and readability. the assembly lang uage, which takes full advantage of the processors unique architecture, offers the follow- ing benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arith- metic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles in to a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relocated to utilize on-chip memory and conform to the adsp-218xls interrupt vect or and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operat ion executed in the same instruction cycle. ? multifunction instructions a llow parallel execution of an arithmetic instruction, with up to two fetches or one write to processor memory space, during a single instruction cycle. development system analog devices wide range of software and hardware development tools supports th e adsp-218xl series. the dsp tools include an integrated deve lopment environment, an evalu- ation kit, and a serial port emulator. visualdsp++ ? ? is an integrated development environment, allowing for fast and easy development, debugging, and deploy- ment. the visualdsp++ project management environment lets programmers develop and debug an application. this environ- ment includes an easy-to-use a ssembler that is based on an algebraic syntax; an archiver (lib rarian/library builder); a linker; a prom-splitter utility; a cycle-accurate, instruction-level simu- lator; a c compiler; and a c run-time library that includes dsp and mathematical functions. debugging both c and asse mbly programs with the visualdsp++ debugger, programmers can: ? view mixed c and assembly code (interleaved source and object information) ? insert break points ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? fill and dump memory ? source level debugging the visualdsp++ ide lets programmers define and manage dsp software development. th e dialog boxes and property pages let programmers configure and manage all of the adsp-218xl development tools, in cluding the syntax highlight- ing in the visualdsp++ editor. th is capability co ntrols how the development tools process inputs and generate outputs. the adsp-2189m ez-kit lite ? ? provides developers with a cost-effective method for initial evaluation of the powerful adsp-218xl dsp family ar chitecture. the adsp-2189m ez-kit lite includes a standalone adsp-2189m dsp board supported by an evaluation suit e of visualdsp++. with this ez-kit lite, users can learn about dsp hardware and software development and evaluate potential applications of the adsp-218xl series. the adsp-2189m ez-kit lite provides an evaluation suite of the visual dsp++ developmen t environment with the c compiler, assembler, and linker. the size of the dsp executable that can be built using the ez-kit lite tools is lim- ited to 8k words. the ez-kit lite includes the following features: ? 75 mhz adsp-2189m ? full 16-bit stereo audio i/o with ad73322 codec ? rs-232 interface ?ez-ice ? connector for emulator control ?dsp demonstration programs ? evaluation suite of visualdsp++ the adsp-218x ez-ice emulator provides an easier and more cost-effective method for engin eers to develop and optimize dsp systems, shortening product development cycles for faster time-to-market. adsp-218xl seri es members integrate on-chip emulation support with a 14-pin ice-port tm interface. this interface provides a simpler ta rget board connection that requires fewer mechanical clearance considerations than other adsp-2100 family ez-ices. adsp-218xl series members need not be removed from the target system when using the ez-ice, nor are any adapters needed. due to the small footprint of the ez-ice connector, emulation can be supported in final board designs.the ez-ice performs a full range of functions, including: ? in-target operation ? up to 20 breakpoints ? single-step or full-speed operation ? registers and memory values can be examined and altered ? pc upload and download functions ? instruction-level emulation of program booting and execution ? visualdsp++ is a registered trademark of analog devices, inc. ? ez-kit lite is a registered trademark of analog devices, inc. ez-ice is a registered trademark of analog devices, inc.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 15 of 48 | january 2008 ? complete assembly and di sassembly of instructions ? c source-level debugging designing an ez-ice-compatible system adsp-218xl series members have on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system pr ocessor by using only a 14-pin connection from the target system to the ez-ice. target sys- tems must have a 14-pin connector to accept the ez-ices in- circuit probe, a 14-pin plug. issuing the chip reset command during emulation causes the dsp to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. if a passive method of maintaining mode information is being used (as discussed in setting memory mode on page 4 ), it does not matter that the mode information is latched by an emulator reset. however, if the reset pin is being used as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. one method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in figure 13 . this circuit forces the value located on the mode a pin to logic high, regardless of whether it is latched via the reset or ereset pin. the ice-port interface consists of the following adsp-218xl pins: ebr , eint , ee, ebg , eclk, ereset , elin, ems , and elout. these adsp-218xl pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull- down resistors. the traces for these signals between the adsp-218xl and the conn ector must be kept as short as possi- ble, no longer than 3 inches. the following pins are also used by the ez-ice: br , bg , reset , and gnd. the ez-ice uses the ee (emulator enable) signal to take control of the adsp-218xl in the target system. this causes the proces- sor to use its ereset , ebr , and ebg pins instead of the reset , br , and bg pins. the bg output is three-stated. these signals do not need to be jumper -isolated in the system. the ez-ice connects to the target system via a ribbon cable and a 14-pin female plug. the female plug is plugged onto the 14- pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 14 . this connector must be added to the target board design to use the ez-ice. be sure to allow enough room in the system to fit the ez-ice probe onto the 14-pin connector. the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tionpin 7 must be removed from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 0.1 inch. the pin strip he ader must have at least 0.15 inch clearance on all sides to accept th e ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. target memory interface for the target system to be compatible with the ez-ice emula- tor, it must comply with the following memory interface guidelines: design the program memory (p m), data memory (dm), byte memory (bm), i/o memory (iom), and composite memory (cm) external interfaces to comply with worst-case device timing requirements and switching characteristics as specified in this data sheet. the perf ormance of the ez-ice may approach published worst-case specification for some memory access timing requirements and switching characteristics. note: if the target does not meet the worst-case chip specifica- tion for memory access parameters, the circuitry may not be able to be emulated at the de sired clkin frequency. depending on the severity of the specificat ion violation, th e system may be difficult to manufacture, as dsp components statistically vary in switching characteristic and timing requirements, within pub- lished limits. restriction: all memory strobe si gnals on the adsp-218xl (rd , wr , pms , dms , bms , cms , and ioms ) used in the target system must have 10 k pull-up resistors connected when the ez-ice is being used. the pu ll-up resistors are necessary figure 13. mode a pin/ez-ice circuit programmable i/o mode a/pf0 reset ereset adsp-218xl 1k figure 14. target board connector for ez-ice 1 2 3 4 56 7 8 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset
rev. c | page 16 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed when the ez-ice is not being used. target system interface signals when the ez-ice board is instal led, the performance on some system signals changes. design th e system to be compatible with the following system in terface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay between the target circuitry and the dsp on the reset signal. ? ez-ice emulation introduces an 8 ns propagation delay between the target circuitry and the dsp on the br signal. ? ez-ice emulation ignores reset and br , when single-stepping. ? ez-ice emulation ignores reset and br when in emula- tor space (dsp halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsps external memory bus only if bus grant (bg ) is asserted by the ez-ice boards dsp. additional information this data sheet provides a ge neral overview of adsp-218xl series functionality. for addition al information on the architec- ture and instruction set of the processor, refer to the adsp-218x dsp hardware reference and the adsp-218x dsp instruction set reference .
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 17 of 48 | january 2008 pin descriptions adsp-218xl series members are available in a 100-lead lqfp package and a 144-ball bga package. in order to maintain max- imum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functi onality. the external bus pins are configured during reset only, while serial port pins are software configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functionality is reconfigurable, the default state is shown in plain text in table 9 , while alternate functionality is shown in italics . table 9. common-mode pins pin name no. of pins i/o function reset 1 i processor reset input br 1ib u s r e q u e s t i n p u t bg 1 o bus grant output bgh 1 o bus grant hung output dms 1 o data memory select output pms 1 o program memory select output ioms 1 o memory select output bms 1 o byte memory select output cms 1 o combined memory select output rd 1 o memory read enable output wr 1 o memory write enable output irq2 / 1 i edge- or level-sensitive interrupt request 1 pf7 i/o programmable i/o pin irql1 / 1 i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irql0 / 1 i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irqe / 1 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode d 2 / 1 i mode select inputchecked only during reset pf3 i/o programmable i/o pin during normal operation mode c/ 1 i mode select inputchecked only during reset pf2 i/o programmable i/o pin during normal operation mode b/ 1 i mode select inputchecked only during reset pf1 i/o programmable i/o pin during normal operation mode a/ 1 i mode select inputchecked only during reset pf0 i/o programmable i/o pin during normal operation clkin 1 i clock input xtal 1 o quartz crystal output clkout 1 o processor clock output sport0 5 i/o serial port i/o pins sport1/ 5 i/o serial port i/o pins irq1C0 , fi, fo edge- or level-sensitive interrupts, fi, fo 3 pwd 1 i power-down control input pwdack 1 o power-down acknowledge control output fl0, fl1, fl2 3 o output flags v ddint 2ii n t e r n a l v dd (1.8 v) power (lqfp) v ddext 4ie x t e r n a l v dd (1.8 v, 2.5 v, or 3.3 v) power (lqfp) gnd 10 i ground (lqfp)
rev. c | page 18 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l memory interface pins adsp-218xl series members can be used in one of two modes: full memory mode, which allows bdma operation with full external overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. table 10 and table 11 list the active signals at specific pins of the dsp during either of the two operating modes (full memory or host). a signal in on e table shares a pin with a sig- nal from the other table, with the active signal determined by the mode that is set. for the shared pins and their alternate sig- nals (e.g., a4/iad3), refer to the package pinouts in table 29 on page 44 and table 30 on page 45 . v ddint 4ii n t e r n a l v dd (3.3 v) power (bga) v ddext 7ie x t e r n a l v dd (3.3 v) power (bga) gnd 20 i ground (bga) ez-port 9 i/o for emulation use 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, the dsp will ve ctor to the appropriate interrupt vector address when the pin is asserted, either by exte rnal devices or set as a programmable flag. 2 this mode applies to the adsp-2187l only. 3 sport configuration determined by the dsp syst em control register. software configurable. table 9. common-mode pins (continued) pin name no. of pins i/o function table 10. full memory mode pins (mode c = 0) pin name no. of pins i/o function a13C0 14 o address output pins for program, data, byte, and i/o spaces d23C0 24 i/o data i/o pins for program, data, byte, and i/o spaces (8 msbs are also used as byte memory addresses.) table 11. host mode pins (mode c = 1) pin name no. of pins i/o function iad15C0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data, or byte access 1 d23C8 16 i/o data i/o pins for program, data, byte, and i/o spaces iwr 1ii d m a w r i t e e n a b l e ird 1 i idma read enable ial 1 i idma address latch pin is 1ii d m a s e l e c t iack 1 o idma port acknowledge configurable in mode d 2 ; open drain 1 in host mode, external peripheral addr esses can be decoded using the a0, cms , pms , dms , and ioms signals. 2 mode d function available on adsp-2187l only.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 19 of 48 | january 2008 terminating unused pins table 12 shows the recommendations for terminating unused pins. table 12. unused pin terminations pin name 1 i/o 3-state (z) 2 reset state high-z 3 caused by unused configuration xtal o o float clkout o o float 4 a13C1 or o (z) high-z br , ebr float iad12C0 i/o (z) high-z is float a0 o (z) high-z br , ebr float d23C8 i/o (z) high-z br , ebr float d7 or i/o (z) high-z br , ebr float iwr ii h i g h ( i n a c t i v e ) d6 or i/o (z) high-z br , ebr float ird iib r , ebr high (inactive) d5 or i/o (z) high-z float ial i i low (inactive) d4 or i/o (z) high-z br , ebr float is ii h i g h ( i n a c t i v e ) d3 or i/o (z) high-z br , ebr float iack float d2C0 or i/o (z) high-z br , ebr float iad15C13 i/o (z) high-z is float pms o (z) o br , ebr float dms o (z) o br , ebr float bms o (z) o br , ebr float ioms o (z) o br , ebr float cms o (z) o br , ebr float rd o (z) o br , ebr float wr o (z) o br , ebr float br ii h i g h ( i n a c t i v e ) bg o (z) o ee float bgh oo f l o a t irq2 / pf7 i/o (z) i input = high (inactive) or program as output, set to 1, let float 5 irql1 / pf6 i/o (z) i input = high (inactive) or program as output, set to 1, let float 5 irql0 / pf5 i/o (z) i input = high (inactive) or program as output, set to 1, let float 5 irqe / pf4 i/o (z) i input = high (inactive) or program as output, set to 1, let float 5 pwd ii h i g h sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low tfs0 i/o i high or low dt0 o o float
rev. c | page 20 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l sclk1 i/o i input = high or low, output = float rfs1/irq0 i/o i high or low dr1/fi i i high or low tfs1/irq1 i/o i high or low dt1/fo o o float ee i i float ebr ii f l o a t ebg oo f l o a t ereset ii f l o a t ems oo f l o a t eint ii f l o a t eclk i i float elin i i float elout o o float 1 clkin, reset , and pf3C0/mode dCa are not included in th is table because thes e pins must be used. 2 all bidirectional pins have three-stated outp uts. when the pin is configured as an outp ut, the output is high-z (high impedance ) when inactive. 3 high-z = high impedance. 4 if the clkout pin is not used, turn it off, usin g clkodis in sport0 auto buffer control register. 5 if the interrupt/programmable flag pins are no t used, there are two options: option 1: when these pins are configured as inputs at reset and function as interrupts and input flag pins, pull the pins high (inactive). option 2: program the unused pins as outputs, set them to 1 prior to enabling i nterrupts, and let pins float. table 12. unused pin terminations (continued) pin name 1 i/o 3-state (z) 2 reset state high-z 3 caused by unused configuration
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 21 of 48 | january 2008 specifications operating conditions electrical characteristics parameter 1 1 specifications subject to change without notice. k grade (commercial) b grade (industrial) unit min max min max v dd 3.0 3.6 3.0 3.6 v t amb 0 + 7 0C 4 0 + 8 5 c k and b grades parameter 1 1 specifications subject to change without notice. description test conditions min typ max unit v ih hi-level input voltage 2, 3 2 bidirectional pins: d23C0, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a13C1, pf7C0. 3 input only pins: clkin, reset , br , dr0, dr1, pwd . @ v dd = max @ v dd = max 2.0 2.2 v v v il lo-level input voltage 2, 3 @ v dd = min 0.8 v v oh hi-level output voltage 2, 4, 5 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2Cfl0, bgh . 5 although specified for ttl outputs, all adsp-218xl outputs are cmos-compatible and will drive to v dd and gnd, assumi ng no dc loads. @ v dd = min, i oh = C0.5 ma @ v dd = min, i oh = C100 a 6 6 guaranteed but not tested. 1.35 v dd C 0.3 v v v ol lo-level output voltage 2, 4, 5 @ v dd = min, i ol = 2.0 ma 0.4 v i ih hi-level input current 3 @ v dd = max, v in = v dd max 10 a i il lo-level input current 3 @ v dd = max, v in = 0 v 10 a i ozh three-state leakage current 7 7 three-statable pins: a13Ca1, d23Cd0, pms , dms , bms, ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf7Cpf0. @ v dd = max, v in = v dd max 8 8 0 v on br . 10 a i ozl three-state leakage current 7 @ v dd = max, v in = 0 v 8 10 a c i input pin capacitance 3, 6 @ v in = 3.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 9 9 output pin capacitance is th e capacitive load for any three-stated output pin. @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf
rev. c | page 22 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l absolute maximum ratings stresses greater than those list ed below may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions greater than those indicated in the operat ional sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package information the information presented in figure 15 provides details about the package branding for the adsp-218xl processors. for a complete listing of pr oduct availability, see ordering guide on page 47 . esd sensitivity timing specifications general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, parameters cannot be added up meaningfully to derive longer times. timing notes switching characteristics specif y how the processor changes its signals. designers have no cont rol over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristic s. switching characteristics tell what the processor will do in a given circumstance. switching characteristics can also be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to si gnals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. frequency dependency for timing specifications t ck is defined as 0.5 t cki . the adsp-218xl uses an input clock with a frequency equal to half th e instruction rate. for example, a 26 mhz input clock (which is equivalent to 38 ns) yields a 19 ns processor cycle (equivalent to 52 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain the specification value. example: t ckh = 0.5 t ck C 7 ns = 0.5 (19) C 7 ns = 2.5 ns parameter rating supply voltage (v dd )C 0 . 3 v t o + 4 . 6 v input voltage 1 1 applies to bidirectional pins (d23C0, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a13C1, pf7C0) and input only pins (clkin, reset , br , dr0, dr1, pwd ). C0.5 v to v dd + 0.5 v output voltage swing 2 2 applies to output pins (bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2C0, bgh ). C0.5 v to v dd +0.5 v operating temperature range C40c to +85c storage temperature range C65c to +150c figure 15. typical package brand table 13. package br and information brand key field description t temperature range pp package type z rohs compliant option (optional) cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code vvvvvv.x n.n tppz-cc adsp-218xl a yyww country_of_origin esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 23 of 48 | january 2008 clock signals and reset table 14. clock signals and reset adsp-2184l, adsp-2186l adsp-2185l, adsp-2187l parameter min max min max unit timing requirements: t cki clkin period 50 150 38 100 ns t ckil clkin width low 20 15 ns t ckih clkin width high 20 15 ns switching characteristics: t ckl clkout width low 0.5t ck C 7 0.5t ck C 7 ns t ckh clkout width high 0.5t ck C 7 0.5t ck C 7 ns t ckoh clkin high to clkout high 0 20 0 20 ns control signals timing requirements: t rsp reset width low 1 5t ck 5t ck ns t ms mode setup before reset high 2 2 ns t mh mode hold after reset high 5 5 ns 1 applies after power-up sequence is complete . internal phase lock loop requ ires no more than 2000 cl kin cycles, assuming stable clkin (not including crystal oscillator start-up time). figure 16. clock signals and reset t ckoh t cki t ckih t ckil t ckh t ckl t mh t ms clkin clkout mode a d reset t rsp
rev. c | page 24 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l interrupts and flags table 15. interrupts and flags parameter min max unit timing requirements: t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25t ck + 15 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25t ck ns switching characteristics: t foh flag output hold after clkout low 5 0.5t ck C 5 ns t fod flag output delay from clkout low 5 0.5t ck + 4 ns 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on t he following cycle. (refer to inte rrupt controller operation in the program control chapter of the adsp-218x dsp hardware reference for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts mus t be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqle . 4 pfx = pf0, pf1, pf2, pf3, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, fl0, fl1, fl2, fo. figure 17. interrupts and flags t fod t foh t ifh t ifs clkout flag outputs irqx fi pfx
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 25 of 48 | january 2008 bus requestCbus grant table 16. bus requestbus grant parameter min max unit timing requirements: t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 17 ns switching characteristics: t sd clkout high to xms , rd , wr disable 2 0.25t ck + 10 ns t sdb xms , rd , wr disable to bg low 0 ns t se bg high to xms , rd , wr enable 0 ns t sec xms , rd , wr enable to clkout high 3 0.25t ck C 7 ns t sdbh xms , rd , wr disable to bgh low 4 0n s t seh bgh high to xms , rd , wr enable 4 0n s 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherw ise the signal will be recogniz ed on the following cycle. refer to the adsp-2100 family users manual for br /bg cycle relationships. 2 xms = pms , dms , cms , ioms , bms . 3 for the adsp-2187l, this specificatio n is 0.25t ck C 4 ns min. 4 bgh is asserted when the bus is granted and the proces sor or bdma requires control of the bus to continue. figure 18. bus requestbus grant clkout t sd t sdb t se t sec t sdbh t seh t bs br t bh clkout pms , dms bms , rd cms , wr, ioms bg bgh
rev. c | page 26 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l memory read table 17. memory read parameter min max unit timing requirements: t rdd rd low to data valid 1 0.5t ck C 9 + w ns t aa a13C0, xms to data valid 2 0.75t ck C 12.5 + w ns t rdh data hold from rd high 3 1n s switching characteristics: t rp rd pulse width 0.5t ck C 5 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 7 ns t asr a13C0, xms setup before rd low 0.25t ck C 6 ns t rda a13C0, xms hold after rd deasserted 0.25t ck C 3 ns t rwr rd high to rd or wr low 0.5t ck C 5 ns 1 w = wait states t ck . 2 xms = pms , dms , cms , ioms , bms . 3 for the adsp-2187l, this sp ecification is 0 ns min. figure 19. memory read clkout address lines 1 data lines 2 t rda t rwr t rp t asr t crd t rdd t aa t rdh dms , pms , bms , ioms , cms rd wr 1 address lines for accesses are: 2 data lines for accesses are: bdma: a13?0 (14 lsbs), d23?16 (8 msbs) bdma: d15?8 i/o space: a10?0 i/o space: d23?8 external pm and dm: a13?0 external dm: d23?8 external pm: d23?0
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 27 of 48 | january 2008 memory write table 18. memory write parameter min max unit switching characteristics: t dw data setup before wr high 1 0.5t ck C 7 + w ns t dh data hold after wr high 0.25t ck C 2 ns t wp wr pulse width 0.5t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a13C0, xms setup before wr low 2 0.25t ck C 6 ns t ddr data disable before wr or rd low 0.25t ck C 7 ns t cwr clkout high to wr low 0.25t ck C 5 0.25t ck + 7 ns t aw a13C0, xms setup before wr deasserted 0.75t ck C 9 + w ns t wra a13C0, xms hold after wr deasserted 0.25t ck C 3 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns 1 w = wait states t ck . 2 xms = pms , dms , cms , ioms , bms . figure 20. memory write clkout t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms , pms , bms , cms , ioms rd wr 1 address lines for accesses are: 2 data lines for accesses are: bdma: a13?0 (14 lsbs), d23?16 (8 msbs) bdma: d15?8 i/o space: a10?0 i/o space: d23?8 external pm and dm: a13?0 external dm: d23?8 external pm: d23?0 address lines 1 data lines 2
rev. c | page 28 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l serial ports table 19. serial ports parameter min max unit timing requirements: t sck sclk period 1 50 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 2 8n s t scp sclkin width 3 20 ns switching characteristics: t cc clkout high to sclkout 0.25t ck 0.25t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 14 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns 1 for the adsp-2187l, this sp ecification is 38 ns min. 2 for the adsp-2187l, this sp ecification is 7 ns min. 3 for the adsp-2185l, and the adsp-2187l , this specification is 15 ns min.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 29 of 48 | january 2008 figure 21. serial ports clkout sclk tfs out rfs out dt alternate fram e mode t cc t cc t sc s t sc h t rh t scde t scd h t scdd t tde t rdv multichannel mode, frame delay 0 (mfd = 0) dr tfs in rfs in rfs out tfs out t tdv t sc d v t rd t scp t sck tfs in rfs in alternate frame mo de t rdv multichannel mode, frame delay 0 (mfd = 0) t tdv t tde t sc p
rev. c | page 30 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l idma address latch table 20. idma address latch parameter min max unit timing requirements: t ialp duration of address latch 1, 2 10 ns t iasu iad15C0 address setup before address latch end 2 5n s t iah iad15C0 address hold after address latch end 2, 3 3n s t ika iack low before start of address latch 2, 4 0n s t ials start of write or read after address latch end 2, 4 3n s t iald address latch start after address latch end 1, 2 2n s 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 for the adsp-2187l, this sp ecification is 2 ns min. 4 start of write or read = is low and iwr low or ird low. figure 22. idma address latch iack ial is iad15?0 ird or iwr t ika t ialp t iasu t iah t iasu t ials t iah t ialp t iald
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 31 of 48 | january 2008 idma write, short write cycle table 21. idma write, short write cycle parameter min max unit timing requirements: t ikw iack low before start of write 1 0n s t iwp duration of write 1, 2 15 ns t idsu iad15C0 data setup before end of write 2, 3, 4 5n s t idh iad15C0 data hold after end of write 2, 3, 4 2n s switching characteristic: t ikhw start of write to iack high 5 17 ns 1 start of write = is low and iwr low. 2 end of write = is high or iwr high. 3 if write pulse ends before iack low, use specifications t idsu , t idh . 4 if write pulse ends after iack low, use specifications t iksu , t ikh . 5 for the adsp-2185l, and the adsp -2187l, this specif ication is 4 ns mi n., and 15 ns max. figure 23. idma write, short write cycle iad15?0 data t ikhw t ikw t id su iack t iwp t idh is iwr
rev. c | page 32 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l idma write, long write cycle table 22. idma write, long write cycle parameter min max unit timing requirements: t ikw iack low before start of write 1 0n s t iksu iad15C0 data setup before end of write 2, 3, 4 0.5t ck + 10 ns t ikh iad15C0 data hold after end of write 2, 3, 4 2n s switching characteristics: t iklw start of write to iack low 4 1.5t ck ns t ikhw start of write to iack high 5 17 ns 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family users manual . 5 for the adsp-2185l, and the adsp -2187l, this specification is 4 ns min., and 15 ns max. figure 24. idma write, long write cycle iad15 ?0 data t ikhw t ikw iack is iwr t iklw t ikh t iksu
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 33 of 48 | january 2008 idma read, long read cycle table 23. idma read, long read cycle parameter min max unit timing requirements: t ikr iack low before start of read 1 0n s t irk end of read after iack low 2 2n s switching characteristics: t ikhr iack high after start of read 1, 3 17 ns t ikds iad15C0 data setup before iack low 0.5t ck C 10 ns t ikdh iad15 C0 data hold after end of read 2 0n s t ikdd iad15C0 data disabled after end of read 2 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 4 15 ns t irdh1 iad15C0 previous data hold after start of read (dm/pm1) 5 2t ck C 5 ns t irdh2 iad15C0 previous data hold after start of read (pm2) 6 t ck C 5 ns 1 start of read = is low and ird low. 2 end of read = is high or ird high. 3 for the adsp-2185l, and the adsp -2187l, this specif ication is 4 ns mi n., and 15 ns max. 4 for the adsp-2187l, this sp ecification is 10 ns max. 5 dm read or first half of pm read. 6 second half of pm read. figure 25. idma read, long read cycle t irk t ikr previous data read data t ikhr t ikds t irdv t ikdd t irde t ikdh iad15?0 iack is ird t irdh1 or t irdh2
rev. c | page 34 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l idma read, short read cycle table 24. idma read, short read cycle parameter 1, 2 min max unit timing requirements: t ikr iack low before start of read 3 0n s t irp1 duration of read (dm/pm1) 4, 5 15 ns t irp2 duration of read (pm2) 6, 7 15 ns switching characteristics: t ikhr iack high after start of read 3 15 ns t ikdh iad15C0 data hold after end of read 8 0n s t ikdd iad15C0 data disabled after end of read 8 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 15 ns 1 short read only must be disabled in the idma overlay memory mapped register. th is mode is disabled by clearing (=0) bit 14 of t he idma overlay register, and is disabled by default upon reset. 2 consider using the short read only mode, instead, because short read mode is no t applicable at high clock frequencies. 3 start of read = is low and ird low. 4 dm read or first half of pm read. 5 for the adsp-2186l, this specific ation also has a max value of 2t ck C 5. 6 second half of pm read. 7 for the adsp-2186l, this specific ation also has a max value of t ck C 5 max. 8 end of read = is high or ird high. figure 26. idma read, short read cycle t irpx t ikr previous data t ikhr t ir dv t ikdd t irde t ikdh iad15?0 iack is ird
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 35 of 48 | january 2008 idma read, short read cycle in short read only mode table 25. idma read, short read cycle in short read only mode 1 parameter 2 min max unit timing requirements: t ikr iack low before start of read 3 0n s t irp duration of read 4 10 ns switching characteristics: t ikhr iack high after start of read 3 10 ns t ikdh iad15C0 previous data hold after end of read 4 0n s t ikdd iad15C0 previous data disabled after end of read 4 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 10 ns 1 applies to the adsp-2187l only. 2 short read only is enabled by setting bit 14 of the idma overlay register to 1 (0x3fe7). short read only can be enabled by the processor core writing to the register or by an external host writing to the register. disabled by default. 3 start of read = is low and ird low. previous data remains until end of read. 4 end of read = is high or ird high. figure 27. idma read, short read cycle in short read only mode t irp t ik r previous data t ikhr t ir d v t ikdd t irde t ikdh iad15?0 iack is ird legend: implies that is and ird can be held indefinitely by host
rev. c | page 36 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l power supply current table 26. power supply current 1 parameter test conditions min typ max unit adsp-2184l i dd supply current (idle) 2 @ v dd = 3.3 v 4 8.6 ma i dd supply current (dynamic) 3 @ v dd = 3.3, t amb = 25 c, t ck = 25 ns 4 42 ma adsp-2185l i dd supply current (idle) 2 @ v dd = 3.3 v 4 t ck = 19 ns t ck = 25 ns t ck = 30 ns 8.6 7.0 6.0 ma ma ma i dd supply current (dynamic) 3 @ v dd = 3.3 v, t amb = 25 c 4 t ck = 19 ns t ck = 25 ns t ck = 30 ns 49 38 31.5 ma ma ma adsp-2186l i dd supply current (idle) 2 @ v dd = 3.3 v 4 8.6 ma i dd supply current (dynamic) 3 @ v dd = 3.3 v, t amb = 25 c, t ck = 25 ns 4 42 ma adsp-2187l i dd supply current (idle) 2 @ v dd = 3.3 v 4 t ck = 19 ns t ck = 25 ns t ck = 30 ns 10 8 7 ma ma ma i dd supply current (dynamic) 3 @ v dd = 3.3 v, t amb = 25 c 4 t ck = 19 ns t ck = 25 ns t ck = 30 ns 51 41 34 ma ma ma 1 specifications subject to change without notice. 2 idle refers to adsp-218xl state of operation during executio n of idle instruction. deasserted pins are driven to either v dd or gnd. 3 i dd measurement taken with all instructions ex ecuting from internal memory. 50% of the in structions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 4 v in = 0 v and 3 v.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 37 of 48 | january 2008 power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f where: c is load capacitance. f is the output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is acce ssed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? application operates at v dd = 3.3 v and t ck = 30 ns. total power di ssipation = p int + ( c v dd 2 f) where: p int is the internal power dissipation from figure 28 through figure 31 on page 39 . (c v dd 2 f) is calculated for each ou tput, as in the example in table 27 . table 27. example power dissipation calculation 1 parameters no. of pins c (pf) v dd 2 (v) f (mhz) pd (mw) address, dms 81 03 . 3 2 33.3 29.0 data output, wr 91 03 . 3 2 16.67 16.3 rd 11 03 . 3 2 16.67 1.8 clkout 1 10 3.3 2 33.3 3.6 = 50.7 1 total power dissipation for this example is p int + 50.7 mw.
rev. c | page 38 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l figure 28. power vs. frequency (adsp-2184l) 10 p o w e r ( p i d l e n ) ? m w 22mw 10mw 9mw idle( 16) 1/ t ck ?mhz 15 20 25 30 35 5 16 p o w e r ( p i d l e ) ? m w 1/ t ck ?mhz 18 20 22 24 26 28 1/ t ck ?mhz 32 30 p o w e r (p i n t ) ? m w 80 34 36 38 40 42 110 120 130 140 150 160 90 100 not es valid for all temperature grades. 1. power reflects device operating with no output loads. 2. ty pical powe r dissi patio n at 3. 3v v dd and 25 c, ex cept where spe ci fi ed. 3. idd measurement taken with all instruct ions executing from internal memory. 50% of the instructions are multifuncti on ( ty pes 1, 4 , 5 , 12 , 13 , 14 ), 30 % are typ e 2 and type 6, and 20% are idle instructions. 4. idle refersto state of operation during execution of idle instruction. deasserted pins are driven to either v d d or gnd. 1 26mw 169mw 139 mw 10 2mw 83mw 11 3mw 32 34 36 38 35 mw 28mw 27mw 22mw 22mw 17mw v d d i n t = 3 . 0 v 12 mw i dl e( 128 ) 13mw 28mw v dd core = 1.9v v dd core = 1.8v power, internal 1, 2, 3 power, idle 1, 2, 4 power, idle n modes 2 170 32 30 34 36 38 40 42 v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v 32 30 34 36 38 40 42 v d d i n t = 3 . 0 v v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v figure 29. power vs. frequency (adsp-2185l) 10 p o w e r ( p i d l e n ) ? m w 20 mw 10m w 9mw 1/ t ck ?mhz 15 20 25 30 35 5 16 p o w e r ( p i d l e ) ? m w 1/ t ck ?mhz 18 20 22 24 26 28 1/ t ck ?mhz 30 p o w e r (p i n t ) ? m w 50 35 40 45 50 55 110 130 150 170 190 210 70 90 not es valid for all temperature g rades. 1. pow er reflects de vice o perating wi th no output loads. 2.typical power dissipation at 3.3v v dd and 25 c, ex cept where spe ci fi ed. 3. idd measurement taken w ith all instructi ons executing from internal memory. 50% of the instructions are m ultifuncti on (ty pes 1, 4 , 5 , 12 , 13, 14 ), 30% are typ e 2 and type 6, and 20% are idle instructions. 4. idle refersto state of operation during execution of idle i ns truction. deass erte d pi ns are dri ven to e ither v d d or g nd. 128mw 19 7mw 161mw 104mw 84mw 13 0mw 30 32 34 36 35mw 22mw 25mw 20mw 28mw 16mw v d d i n t = 3 . 0 v 12 mw 13mw 28 mw power, internal 1, 2, 3 power, idle 1, 2, 4 power, idle n modes 2 230 v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v 30 35 40 45 50 55 30 35 40 45 50 55 40 45 idle(12 8) idle (1 6) v d d i n t = 3 . 0 v v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 39 of 48 | january 2008 figure 30. power vs. frequency (adsp-2186l) 10 p o w e r ( p i d l e n ) ? m w 22mw 10mw 9mw 1/ t ck ?mhz 15 20 25 30 35 5 16 p o w e r (p id l e ) ? m w 1/ t ck ?mhz 18 20 22 24 26 28 1/ t ck ?mhz 32 30 p o w e r (p i n t ) ? m w 80 34 36 38 40 42 110 120 130 140 150 160 90 100 not es valid for all temperature g rades . 1. power reflects de vice ope rating with no output loads. 2. ty pical powe r dissi patio n at 3. 3v v dd and 25 c, ex cept where spe ci fi ed. 3. idd measurement taken with all instruct ions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 4. idle refersto state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 126mw 169mw 139 mw 10 2mw 83mw 113mw 32 34 36 38 35mw 28mw 27mw 22mw 22mw 19mw v d d i n t = 3 . 0 v 12 mw 13mw 28mw v dd core = 1.9v v dd core = 1.8v power, internal 1, 2, 3 power, idle 1, 2, 4 power, idle n modes 2 170 32 30 34 36 38 40 42 v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v 32 30 34 36 38 40 42 idle ( 16) idle(128) v d d i n t = 3 . 0 v v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v figure 31. power vs. frequency (adsp-2187l) 10 p o w e r ( p i d l e n ) ? m w 23 mw 10m w 9mw idle(16) 1/ t ck ?mhz 15 20 25 30 35 5 16 p o w e r ( p i d l e ) ? m w 1/ t ck ?mhz 18 20 22 24 26 28 1/ t ck ?mhz 30 p o w e r (p i n t ) ? m w 50 35 40 45 50 55 110 130 150 170 190 210 70 90 not es valid for all temperature grades. 1. power reflects de vice o perating with no output loads. 2. ty pical powe r dissi patio n at 3. 3v v dd and 25c, except where specified. 3. idd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifuncti on ( ty pes 1, 4 , 5 , 12 , 13, 14 ), 30 % are typ e 2 and type 6, and 20% are idle instructions. 4. idle refersto state of operation during execution of idle instruction. deasserted pins are driven to either v d d or g nd. 144 mw 21 6mw 168.3mw 112.2mw 87mw 13 2mw 30 32 34 36 35mw 32mw 25mw 23mw 30mw 21mw v d d i n t = 3 . 0 v 12 mw idle(128) 13mw 32 mw power, internal 1, 2, 3 power, idle 1, 2, 4 power, idle n modes 2 230 v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v 30 35 40 45 50 55 30 35 40 45 50 55 40 45 idle v d d i n t = 3 . 0 v v d d i n t = 3 . 3 v v d d i n t = 3 . 6 v
rev. c | page 40 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l output drive currents figure 32 through figure 35 show typical i-v characteristics for the output drivers on the adsp -218xl processors. the curves represent the current drive capability of the output drivers as a function of output voltage. figure 32. typical output driver characteristics (adsp-2184l) figure 33. typical output driver characteristics (adsp-2185l) source voltage ? v 00.51.0 s o u r c e c u r r e n t ? m a 60 0 ?20 ?40 ?60 40 20 v ddext = 3.6v @ ?40 c v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ddext =3.6v@?40 c 80 ?80 1.5 2.0 2.5 3.0 3.5 v oh v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ol source voltage ? v 00.51.0 s o u r c e c u r r e n t ? m a 60 0 ?20 ?40 ?60 40 20 v ddext =3.6v@?40 c v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ddext =3.6v@?40 c 80 ?80 1.5 2.0 2.5 3.0 3.5 v oh v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ol 4.0 figure 34. typical output driver characteristics (adsp-2186l) figure 35. typical output driver characteristics (adsp-2187l) source voltage ? v 00.51.0 s o u r c e c u r r e n t ? m a 60 0 ?20 ?40 ?60 40 20 v ddext = 3.6v @ ?40 c v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ddext =3.6v@?40 c 80 ?80 1.5 2.0 2.5 3.0 3.5 v oh v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ol source voltage ? v 00.51.0 s o u r c e c u r r e n t ? m a 60 0 ?20 ?40 ?60 40 20 v ddext =3.6v@?40 c v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ddext =3.6v@?40 c 80 ?80 1.5 2.0 2.5 3.0 3.5 v oh v ddext =3.3v@+25 c v ddext =3.0v@+85 c v ol 4.0
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 41 of 48 | january 2008 power-down current figure 36 through figure 39 show the typical power-down supply current. note that these graphs reflect adsp-218xl operation in lowest power mode. (see the system interface chapter of the adsp-218x dsp hardware reference for details). current reflects device operating with no input loads. figure 36. typical power-down current (adsp-2184l) figure 37. typical power-down current (adsp-2185l) temperature ? c 1000 100 0 08 5 25 55 10 c u r r e n t ( l o g s c a l e ) ? a 10000 v dd =3.6v v dd =3.3v temperature ? c 1000 100 0 08 5 25 55 10 c u r r e n t ( l o g s c a l e ) ? a 10000 v dd =3.6v v dd =3.3v figure 38. typical power-down current (adsp-2186l) figure 39. typical power-down current (adsp-2187l) temperature ? c 1000 100 0 08 5 25 55 10 c u r r e n t ( l o g s c a l e ) ? a 10000 v dd =3.6v v dd =3.3v temperature ? c 1000 100 0 08 5 25 55 10 c u r r e n t ( l o g s c a l e ) ? a 10000 v dd =3.6v v dd =3.3v v dd =3.0v
rev. c | page 42 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l capacitive loading C adsp-2184l, adsp-2186l figure 40 and figure 41 show the capacitive loading characteris- tics of the adsp-2184l and adsp-2186l. capacitive loading C adsp-2185l, adsp-2187l figure 42 and figure 43 show the capacitive loading characteris- tics of the adsp-2185l and adsp-2187l. figure 40. typical ou tput rise time vs. load capacitance (at maximum ambient operating temperature) figure 41. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) c l ?pf r is e t i m e ( 0 . 4 v ? 2 . 4 v ) ? n s 0 40 80 120 180 25 15 10 5 0 20 t=85 c v dd =3.0v 160 200 c l ?pf 14 0 v a l i d o u t p u t d e l a y o r h o l d ? n s 50 100 150 250 200 12 4 2 ?2 10 8 nominal 16 18 6 ?4 ?6 figure 42. typical output rise time vs. load capacitance (at maximum ambient operating temperature) figure 43. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) c l ?pf r is e t i m e ( 0 . 4 v ? 2 . 4 v ) ? n s 0 50 100 150 250 18 12 9 6 0 15 t=85 c v dd =3.0v 200 c l ?pf 0 v a l i d o u t p u t d e l a y o r h o l d ? n s 40 80 120 200 160 12 4 2 ?2 10 8 nominal 6 ?4 ?6
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 43 of 48 | january 2008 test conditions figure 44 shows voltage reference levels for all ac measurements (except output disable/enable). output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a hi gh impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in figure 45 . the time is the interv al from when a refer- ence signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured out- put high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approxi- mated by the following equation: from which is calculated. if multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 45 . if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. environmental conditions figure 44. voltage reference levels for ac measurements (except output enable/disable) 1.5v input or output 1.5v t decay c l 0.5v i l ----------------------- - = t dis t measured t decay ? = figure 45. output enable/disable figure 46. equivalent loading for ac measurements (including all fixtures) table 28. thermal resistance rating description 1 1 where the ambient temperature rating (t amb ) is: t amb = t case C (pd ca ) t case = case temperature in c pd = power dissipation in w symbol lqfp ( c/w) bga ( c/w) thermal resistance (case- to-ambient) ca 48 63.3 thermal resistance (junction-to-ambient) ja 50 70.7 thermal resistance (junction-to-case) jc 27.4 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) ? 0.5v v ol (measured) + 0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) to output pin 50pf 1.5v i oh i ol
rev. c | page 44 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l lqfp package pinout the lqfp package pinout is shown in table 29 . pin names in bold text in the table replace the plain-text-named functions when mode c equals 1. a plus sign (+) separates two functions when either function can be active for either major i/o mode. signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of reset . the multiplexed pins dt1/fo, tfs1/irq1 , rfs1/irq0 , and dr1/fi, are mode selectable by setting bit 10 (spo rt1 configure) of the system control register. if bit 10 = 1, th ese pins have serial port func- tionality. if bit 10 = 0, these pi ns are the extern al interrupt and flag pins. this bit is set to 1 by default, upon reset. table 29. lqfp pin assignments lead no. lead name lead no. lead name lead no. lead name lead no. lead name 1a 4 / iad3 26 irqe + pf4 51 ebr 76 d16 2a 5 / iad4 27 irql0 + pf5 52 br 77 d17 3g n d2 8 g n d 5 3 e b g 78 d18 4a 6 / iad5 29 irql1 + pf6 54 bg 79 d19 5a 7 / iad6 30 irq2 + pf7 55 d0/ iad13 80 gnd 6a 8 / iad7 31 dt0 56 d1/ iad14 81 d20 7a 9 / iad8 32 tfs0 57 d2/ iad15 82 d21 8a 1 0 / iad9 33 rfs0 58 d3/ iack 83 d22 9a 1 1 / iad10 34 dr0 59 v ddint 84 d23 10 a12/ iad11 35 sclk0 60 gnd 85 fl2 11 a13/ iad12 36 v ddext 61 d4/ is 86 fl1 12 gnd 37 dt1/fo 62 d5/ ial 87 fl0 13 clkin 38 tfs1/irq1 63 d6/ ird 88 pf3 [mode d 1 ] 14 xtal 39 rfs1/irq0 64 d7/ iwr 89 pf2 [mode c] 15 v ddext 40 dr1/fi 65 d8 90 v ddext 16 clkout 41 gnd 66 gnd 91 pwd 17 gnd 42 sclk1 67 v ddext 92 gnd 18 v ddint 43 ereset 68 d9 93 pf1 [mode b] 19 wr 44 reset 69 d10 94 pf0 [mode a] 20 rd 45 ems 70 d11 95 bgh 21 bms 46 ee 71 gnd 96 pwdack 22 dms 47 eclk 72 d12 97 a0 23 pms 48 elout 73 d13 98 a1/ iad0 24 ioms 49 elin 74 d14 99 a2/ iad1 25 cms 50 eint 75 d15 100 a3/ iad2 1 mode d function available on adsp-2187l only.
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 45 of 48 | january 2008 bga package pinout the bga package pinout is shown in table 30 . pin names in bold text in the table replace the plain text named functions when mode c equals 1. a plus sign (+) separates two functions when either function can be active for either major i/o mode. signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of reset . the multiplexed pins dt1/fo, tfs1/irq1 , rfs1/irq0 , and dr1/fi, are mode selectable by setting bit 10 (spo rt1 configure) of the system control register. if bit 10 = 1, th ese pins have serial port func- tionality. if bit 10 = 0, these pi ns are the extern al interrupt and flag pins. this bit is set to 1 by default upon reset. table 30. bga pin assignments ball no. ball name ball no. ball name ball no. ball name ball no. ball name a01 a2/ iad1 d01 nc g01 xtal k01 nc a02 a1/ iad0 d02 wr g02 nc k02 nc a03 gnd d03 nc g03 gnd k03 nc a04 a0 d04 bgh g04 a10/ iad9 k04 bms a05 nc d05 a9/ iad8 g05 nc k05 dms a06 gnd d06 pf1 [mode b] g06 nc k06 rfs0 a07 nc d07 pf2 [mode c] g07 nc k07 tfs1/irq1 a08 nc d08 nc g08 d6/ ird k08 sclk1 a09 nc d09 d13 g09 d5/ ial k09 ereset a10 d22 d10 d12 g10 nc k10 ebr a11 gnd d11 nc g11 nc k11 br a12 gnd d12 gnd g12 d4/ is k12 ebg b01 a4/ iad3 e01 v ddext h01 clkin l01 irqe + pf4 b02 a3/ iad2 e02 v ddext h02 gnd l02 nc b03 gnd e03 a8/ iad7 h03 gnd l03 irql1 + pf6 b04 nc e04 fl0 h04 gnd l04 ioms b05 nc e05 pf0 [mode a] h05 v ddint l05 gnd b06 gnd e06 fl2 h06 dt0 l06 pms b07 v ddext e07 pf3 [mode d 1 ]h07 tfs0 l07 dr0 b08 d23 e08 gnd h08 d2/ iad15 l08 gnd b09 d20 e09 gnd h09 d3/ iack l09 reset b10 d18 e10 v ddext h10 gnd l10 elin b11 d17 e11 gnd h11 nc l11 elout b12 d16 e12 d10 h12 gnd l12 eint c01 pwdack f01 a13/ iad12 j01 clkout m01 irql0 + pf5 c02 a6/ iad5 f02 nc j02 v ddint m02 irql2 + pf7 c03 rd f03 a12/ iad11 j03 nc m03 nc c04 a5/ iad4 f04 a11/ iad10 j04 v ddext m04 cms c05 a7/ iad6 f05 fl1 j05 v ddext m05 gnd c06 pwd f06 nc j06 sclk0 m06 dt1/fo c07 v ddext f07 nc j07 d0/ iad13 m07 dr1/fi c08 d21 f08 d7/ iwr j08 rfs1/irq0 m08 gnd c09 d19 f09 d11 j09 bg m09 nc c10 d15 f10 d8 j10 d1/ iad14 m10 ems c11 nc f11 nc j11 v ddint m11 ee c12 d14 f12 d9 j12 v ddint m12 eclk 1 mode d function availabl e on adsp-2187l only.
rev. c | page 46 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l outline dimensions figure 47. 144-ball bg a [csp_bga] (bc-144-6) figure 48. 100-lead low profile quad flat package [lqfp] (st-100-1) * compliant to jedec standards mo-205-ac with the exception to ball diameter. a1 ball corner top view ball a1 pad corner detail a bottom view 10.10 10.00 sq 9.90 seating plane ball diameter * 0.50 0.45 0.40 coplanarity 0.12 0.80 bsc 0.60 ref 8.80 bsc sq detail a 1.40 1.34 1.19 1.11 1.01 0.91 0.33 nom 0.28 min 101112 8 7 6 3 2 1 9 5 4 a b c d e f g j h k l m compliant to jedec standards ms-026-bed top view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a seating plane 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 max lead coplanarity view a rotated 90 ccw seating plane 7 3.5 0 12.00 ref 16.00 bsc sq 14.00 bsc sq the actual position of each lead is within 0.08 of its ideal position when measured in the lateral direction. 12 typ
adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l rev. c | page 47 of 48 | january 2008 surface mount design table 31 is provided as an aid to pcb design to accommodate bga style surface mount pack ages. for industry-standard design recommendations, refer to ipc-7351, generic require- ments for surface mount design and land pattern standard . ordering guide table 31. bga data for use with surface mount design package ball attach type solder mask opening ball pad size 144-ball bga (bc-144-6) solder mask defined 0.40 mm diameter 0.50 mm diameter model temperature range 1 1 ranges shown represent ambient temperature. instruction rate (mhz) package description package option adsp-2184lbst-160 C40c to +85c 40 100-lead lqfp st-100-1 adsp-2184lbstz-160 2 2 z = rohs compliant part. C40c to +85c 40 100-lead lqfp st-100-1 adsp-2185lkst-115 0c to 70c 28.8 100-lead lqfp st-100-1 adsp-2185lkst-133 0c to 70c 32.2 100-lead lqfp st-100-1 adsp-2185lkst-160 0c to 70c 40 100-lead lqfp st-100-1 adsp-2185lkst-210 0c to 70c 52.5 100-lead lqfp st-100-1 adsp-2185lkstz-210 2 0c to 70c 52.5 100-lead lqfp st-100-1 adsp-2185lbst-115 C40c to +85c 28.8 100-lead lqfp st-100-1 adsp-2185lbst-133 C40c to +85c 32.2 100-lead lqfp st-100-1 adsp-2185lbstz-133 2 C40c to +85c 32.2 100-lead lqfp st-100-1 adsp-2185lbst-160 C40c to +85c 40 100-lead lqfp st-100-1 adsp-2185lbstz-160 2 C40c to +85c 40 100-lead lqfp st-100-1 adsp-2185lbst-210 C40c to +85c 52.5 100-lead lqfp st-100-1 adsp-2185lbstz-210 2 C40c to +85c 52.5 100-lead lqfp st-100-1 adsp-2186lkst-115 0c to 70c 28.8 100-lead lqfp st-100-1 adsp-2186lkst-115r 3 3 r = tape and reel. 0c to 70c 28.8 100-lead lqfp st-100-1 adsp-2186lkst-133 0c to 70c 32.2 100-lead lqfp st-100-1 adsp-2186lkstz-133 2 0c to 70c 32.2 100-lead lqfp st-100-1 adsp-2186lbst-115 C40c to +85c 28.8 100-lead lqfp st-100-1 adsp-2186lbstz-115 2 C40c to +85c 28.8 100-lead lqfp st-100-1 adsp-2186lbst-160 2 C40c to +85c 40 100-lead lqfp st-100-1 ADSP-2186LBCA-160R 3 C40c to +85c 40 144-ball bga bc-144-6 adsp-2187lkst-160 0c to 70c 40 100-lead lqfp st-100-1 adsp-2187lkstz-160 2 0c to 70c 40 100-lead lqfp st-100-1 adsp-2187lkst-210 0c to 70c 52.5 100-lead lqfp st-100-1 adsp-2187lkstz-210 2 0c to 70c 52.5 100-lead lqfp st-100-1 adsp-2187lbst-160 C40c to +85c 40 100-lead lqfp st-100-1 adsp-2187lbstz-160 2 C40c to +85c 40 100-lead lqfp st-100-1 adsp-2187lbst-210 C40c to +85c 52.5 100-lead lqfp st-100-1 adsp-2187lbstz-210 2 C40c to +85c 52.5 100-lead lqfp st-100-1
rev. c | page 48 of 48 | january 2008 adsp-2184l/adsp-2185l/adsp-2186l/adsp-2187l ? 2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00192-0-1/08(c)

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